1. Field of the Invention
Example embodiments relate to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device including gate lines.
2. Description of the Related Art
A semiconductor device typically includes numerous transistors. In particular, a semiconductor memory device includes numerous transistors arranged densely and regularly. For example, flash memory includes numerous strings that are arranged regularly. Each of the strings includes a plurality of cell transistors coupled in series between source and drain select transistors. A gate line coupled to the gates of cell transistors is a word line, a gate line coupled to the gates of source select transistors is a source select line, and a gate line coupled to the gates of drain select transistors is a drain select line. In general, an interval between adjacent drain select lines and an interval between adjacent source select lines is wider than an interval between adjacent word lines.
To increase the degree of integration of devices, the width of gate lines are gradually narrowed, thereby increasing the resistance of a gate line. In order to improve the resistance of a gate line, a method of forming the gate lines using a metal silicide layer is used. A silicidation process of forming the metal silicide layer includes etching a multi-layered insulating layer.